During this Fifth lecture about Combinational Logic of Digital Logic and Design, we have explored the design of Binary Multiplier and Magnitude Comparator Circuits. Initially we have discussed the multiplication algorithm with a very simple example. In this example, we have discussed the multiplication of two 2-bit numbers to produce their product of 4 bits. This circuit has been implemented with the help of two and gates and two half adders. Next, we have extended the algorithm for a 4-bit multiplicand and a 3-bit multiplier to produce a multiplication result of 7-bits. In this algorithm we have explained how to extend the algorithm for more number of bits for example if we want to multiply and 8 bit number with yet another 8 bit number then how we can get implement it that has also been explained in that slide. Then we have discussed the algorithm for magnitude comparator. A magnitude comparator is a circuit that compares two n-bit numbers and provides the result whether the numbers are equal or the First Number a is greater than the Second Number or the Second Number is greater than the First Number (i.e. the First Number is less than the Second Number). Although we could have used the classical design approach to design the circuit that we have discussed during the third lecture but that will be too cumbersome so have used the inherent similarity in the comparison and we have obtained a simple as possible algorithm that compares two n bit numbers and provide their comparison result. These Lecture slides are based upon text from the textbook Digital Design [5th Edition] by M. Morris Mano and Michael Ciletti.